This page summarizes all the troublesome issues and corresponding solutions during module assembly and DAQ tests. It is divided into 2 parts: hardware related and software (mainly DAQ) related. Hardware related, for example, includes high leakage current for HV, chipped chips and so on. Software related, includes capturing incorrect chips ID, errors during tests and so on.

Hardware related

High leakage current for HV

  • Description: very high leakage current during IV scan for a module, the HV breaks down very early (below 400 V @10uA).
  • Reason 1: there is scratch on the sensor;
  • Reason 2: the glue between sensor and hybrid is coming out to the edge (guard ring), which cause short;
  • Reason 3: test frame, one way to check it is to remove the HV bond (test frame to hybrid) and HVret bond (powerboard to test frame) sequentially, if there is still high leakage current, it means it is caused by test frame or hybrid.

Software related

Bi-direction readout

  • Description: for one direction, dummy or random chips ID are captured; however, for the other direction, all chips IDs are captured correctly.
  • Solution: adjust the LDOD values in configuration files. This value adjusts the voltage supplied on the chips.

read_bit_data error (timeout stream x)

  • Description: this errors happens during electrical tests, when the packets are not received by the itsdaq. If you check the packets reception with ifconfig in linux, there is no dropped packets.
  • Solution: bandwidth, somehow it's reaching the bandwidth of the computer. To make the tests running, one can hardcode to single trigger for each burst in DAQ. In this case, it will run slowly.
-- Maosen Zhou - 2018-03-07


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Topic revision: r1 - 2018-03-07 - MaosenZhou
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